1. Field of the Invention
Embodiments of the present invention relate generally to a nonvolatile semiconductor memory device. More particularly, embodiments of the invention relate to a nonvolatile semiconductor memory device having a dummy bit line.
This application claims priority to Korean Patent Application No. 10-2005-89188, filed on Sep. 26, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Conventional nonvolatile semiconductor memory devices (hereafter, simply referred to as “memory device(s)”) often incorporate an extra bit line that is not used for the transfer and storage of data, but is instead used to good effect during the fabrication of the semiconductor memory. This type of bit line is commonly referred to as a “dummy bit line. ” In one application, dummy bit lines serve as a connection medium of sorts. That is, certain wiring section(s) (e.g., upper sections) used to form the memory array matrix of the memory device are connected to other wiring sections (e.g., lower sections) through the dummy bit line.
In a more specific example, an upper wiring section (e.g., wiring located above the bit lines) is connected to a lower section (e.g., wiring located below the bit lines) through a dummy bit line, wherein the upper and lower wiring sections comprise a common source line. A source voltage is applied to “normal” memory cells (e.g., memory cells adapted to validly store data in the memory device), connected to normal bit lines (e.g., non-dummy bit lines) through the common source line. In conventional memory devices the voltage applied to the common source line tends to stabilize rather slowly. As a result, the voltage level on the common source line may drop when a normal bit line is used to sense the data stored in a corresponding memory cell.
Of further note, data from a selected normal memory cell is read in accordance with a voltage level on a corresponding normal bit line. Thus, during such read operations it is important to minimize the influence (e.g., coupling noise) of the surrounding wiring on the corresponding normal bit line in order to accurately read the data.
FIG. (FIG.) 1 is a diagram illustrating a portion of a conventional memory device cell array. FIG. 2 is a related layout illustrating normal bit lines (BLs), a dummy bit line (DBL), and a common source line (CSL), such as those show in FIG. 1. Referring collectively to FIGS. 1 and 2, a plurality of normal memory cells (MCs) is connected to the normal bit lines (BLs). Dummy memory cells (DMCs), which unlike normal memory cells are not adapted to store data, are connected to the dummy bit line (DBL). The dummy bit line (DBL) is arranged parallel with the normal bit lines (BLs) and have a similar length. Therefore, high coupling capacitance may be formed between the dummy bit line (DBL) and adjacent normal bit lines (BLs).
Additionally, in the conventional memory device, the dummy bit line (DBL) is connected to the common source line (CSL). (See, point PT11 of FIG. 1 and point PT11 in FIG. 2). In this case, when a normal bit line (BL) senses the data stored in a memory cell (MC), the voltage level on the dummy bit line (DBL) drops significantly. As a result, the voltage levels on normal bit lines adjacent to the dummy bit line (e.g., BL<1,1> and BL<2,1> in the illustrated example) also drop due to capacitive coupling effects. Due to this capacitive coupling effect induced voltage drop on normal bit lines (BLs) adjacent to the dummy bit line (DBL) in conventional memory devices, an OFF-state may be erroneously read (or detected) as a ON-state for a memory cell connected to the normal bit lines (BLs) adjacent to the dummy bit line (DBL).